SATO,Shingo - Faculty of Engineering Science Department of Electrical and Electronic Engineering

SATO, Shingo

Faculty, Department/Institute

Faculty of Engineering Science Department of Electrical and Electronic Engineering

Academic status (qualification)

Associate Professor Apr. 1,2018

Academic Degrees

Mar. 2008 Kansai University

Research fields	keyword
Electron devices

Research Publications

No.	Type of publication	Date of publication (Date of presentation)	Title	Jointly authored or single authored	Publisher and journal name	Volume number
1	Papers1	2019/9～2019/92019,09,00,2019,09,00	Impact of contact and channel resistance on the frequency-dependent capacitance and conductance of pseudo-MOSFET	International coauthorship	Solid State Electronics	Vol. 159, Sep. 2019, pp. 197-203
2	Papers1	2018/12～2018,12,00,,,	Study on the Impacts of Hole Injection and Inclusion of Sub-oxide and Metallic Si Atoms on Repeatable Resistance Switching of Sputter-Deposited Silicon Oxide Films	Co-authored	IEEE Transactions on Device and Materials Reliability	Volume: 18, Issue:4, pp.561-567
3	International academic conference8	2018/9～2018,09,00,,,	Sharp switching, hysteresis-free characteristics of Z2-FET for fast logic applications	International coauthorship	2018 48th European Solid-State Device Research Conference (ESSDERC)	pp.74-77
4	International academic conference8	2018/6～2018,06,00,,,	Aspects and Reduction of Miller Capacitance of Lateral Tunnel FETs	International coauthorship	IEEE IMFEDK (Kyoto, 2018)	pp.22-23
5	International academic conference8	2018/3～2018,03,00,,,	Detailed analysis of frequency-dependent impedance in pseudo-MOSFET on thin SOI film	International coauthorship	Joint International EUROSOI Workshop and International Conference on Ultimate Integration on Silicon	pp. 89-90
6	Papers1	2018/2～2018,02,00,,,	Possible Models of Electron-Energy Transfer in Resistance Switching by Sputter-Deposited Silicon Oxide Films: Potential of Extremely Low-Energy Switching	Co-authored	ECS Journal of Solid State Science and Technology	volume 7, issue 3, Q21-Q25
7	Papers1	2018～2018,00,00,,,	Novel Addressable Test Structure for Detecting Soft Failure of Resistive Elements when Developing Manufacturing Procedures	Co-author	IEEE Transactions on Semiconductor Manufacturing	Vol. 31, Issue. 1, pp.124-129
8	International academic conference8	2018～2018,00,00,,,	Measuring impact of light on resistance of non-doped ZnO films	Co-authored	Advanced NanoMaterials Conf., (Aveiro, Portugal, 2018)	in print
9	Papers1	2017/12～2017,12,00,,,	Revisiting the Role of Trap-Assisted-Tunneling Process on Current-Voltage Characteristics in Tunnel Field-Effect Transistors	International coauthorship	Journal of Applied Physics	vol. 123, pp. 161549-1-161549-6
10	International academic conference8	2017/10～2017,10,00,,,	Physical Mechanisms of Short-Channel Effects of Lateral Double-Gate Tunnel FET	International coauthorship	Proceedings of Nano S & T 2017	p.5525
11	International academic conference8	2017/10～2017,10,00,,,	Theoretical Models for Electron Diffusion Coefficient of One-Dimensional Si Wire Devices: impacts of conduction band non-parabolicity-	Co-authored	Proceedings of Nano S & T 2017	p.338
12	International academic conference8	2017/10～2017,10,00,,,	Important Roles of Hole Injection and Inclusion of Sub-oxide and Metallic Si Atoms on Resistive Transition of Sputter-Deposited Silicon Oxide Films	Co-authored	Proceedings of Nano S & T 2017	pp. 346
13	International academic conference8	2017/10～2017,10,00,,,	Theoretical Models for Low-Frequency Noise Behaviors of Buried-Channel MOSFETs	Co-authored	Proc. IEEE S3S Conference 2017 (Oct., San Francisco)	paper No. 8.11
14	Academic presentation7	2017/10～2017,10,00,,,	Definite Influence of Substrate-contact Condition on SOI Substrate Impedance Parameters	Co-authored	Proc. IEEE S3S Conference 2017 (Oct., San Francisco)	paper No. 8. 7.
15	International academic conference8	2017/9～2017,09,00,,,	Impact of Crystal Orientation and Conduction Band Non-parabolicity on Diffusion Constant of Nano-scale Si Rectangular Wires - theoretical estimation	Co-authored	12th Nanosmat Conf. (Paris, Sept., 2017)	pp. 1-3
16	Papers1	2017/7～2017,07,00,,,	Impact of Native Oxide Growth on the Capacitance-Voltage Characteristic of Pseudo-MOS Structure	Co-authored	ECS Transactions	vol. 77, issue 11, pp. 1887-1892
17	International academic conference8	2017/6～2017,06,00,,,	Physical Mechanisms of Short-Channel Effects of Lateral Double-Gate Tunnel FET	International coauthorship	abstract of IMFEDK 2017	pp. 34-35
18	Papers1	2017/4～2017,04,00,,,	On the Definition of Threshold Voltage for Tunnel FETs	International coauthorship	Superlattices and Microstructures	vol. 107, pp. 17-27
19	Papers1	2017/3～2017,03,00,,,	Roles of chemical stoichiometry and hot electrons in realizing the stable resistive transition of sputter-deposited silicon oxide films	Co-authored	Japanese Journal of Applied Physics	vol. 56, No. 4, pp. 041301-1-041301-6
20	International academic conference8	2017/3～2017,03,00,,,	Impact of native oxide on the capacitance-voltage characteristic for pseudo-MOS structure	Co-authored	The 231st Electrochemical Society Meeting	Abstract MA2017-01, Z01-1959
21	International academic conference8	2017/3～2017,03,00,,,	Recent Progress of Pseudo-MOS Method Used for Evaluating Electrical Properties of the SOI Wafer	Co-authored	Proc. 4th int. Symp. Semicond. Mat. And Devices	pp. 34
22	International academic conference8	2016～2016,00,00,,,	Proposal of a New Array Structure to Enable the Detection of Soft Failure and the Aging Test with Overcurrent of Resistive Element		Proceedings of 29th IEEE International Conference on Microelectronic Test Structures	pp.52-56
23	Papers1	2016～2016,00,00,,,	Proposal of Physics-Based Equivalent Circuit of Pseudo-MOS Capacitor Structure for Impedance Spectroscopy		IEEE Journal of the Electron Devices Society	vol. 4, pp. 169-173
24	International academic conference8	2016～2016,00,00,,,	Stable Unipolar and Bipolar Resistive Transitions of Sputter-Deposited SiO2 Films		Abstracts of 2016 IEEE Silicon Nanoelectronics WS	pp. 74-75
25	International academic conference8	2016～2016,00,00,,,	A Possible Threshold Voltage Definition of Lateral Tunnel FET,	International coauthorship	Abstracts of 2016 IEEE Silicon Nanoelectronics WS	pp. 188-189
26	International academic conference8	2016～2016,00,00,,,	Capacitance Analysis of Pseudo-MOSFET Using Cole-Cole Plots		Tech. Digest of IEEE IMFEDK 2016	pp. 36-37.
27	International academic conference8	2016～2016,00,00,,,	Sensitivity of Resistive Transition of Sputter-Deposited TiO2 Films to Electrode Material		Tech. Dig. of IEEE IMFEDK 2016	pp. 72-73.
28	Papers1	2015～2015,00,00,,,	Possible Theoretical Models for Carrier Diffusion Coefficient of One-Dimensional Si Wire Devices		Japanese Journal of Applied Physics	vol.54, No. 5, p.054001-1-054001-7
29	Papers1	2015～2015,00,00,,,	Compact Modeling for Nano-Wire Tunnel Field-Effect Transistor	International coauthorship	ECS Transactions	vol. 66, No. 5, pp.171-177
30	Papers1	2015～2015,00,00,,,	Analytically Modeling the Asymmetric Double Gate Tunnel FET	International coauthorship	ECS Transactions	vol. 66, No. 5, pp.193-200
31	International academic conference8	2015～2015,00,00,,,	Circuit Architecture and Measurement Technique to Reduce the Leakage Current Stemming from Peripheral Circuits with an Array Structure in Examining the Resistive Element		Proceedings of the 2015 IEEE International Conference on Microelectronic Test Structures	pp.14-17
32	International academic conference8	2015～2015,00,00,,,	Compact Modeling for Nano-Wire Tunnel Field Effect Transistor		227th ECS Meeting, Int. Symp. on Advanced CMOS-Compatible Semiconductor Devices 17th	No. 46297
33	International academic conference8	2015～2015,00,00,,,	An Analytical Modeling for Asymmetric Double-Gate Tunnel FET Operation	International coauthorship	227th ECS Meeting, Int. Symp. on Advanced CMOS-Compatible Semiconductor Devices 17th	No. 49434
34	International academic conference8	2015～2015,00,00,,,	Two-Dimensional Potential Model for Asymmetric Double-Gate Tunnel FET Considering the Source-Channel Junction Depletion Region	International coauthorship	Tech. Dig., IEEE IMFEDK	pp.58-59
35	International academic conference8	2015～2015,00,00,,,	Development of a Compacted Doubly Nesting Array in Narrow Scribe Line Aimed at Detecting Soft Failures of Interconnect Via		28th IEEE International Conference on Microelectronic Test Structures	pp.78-81
36	International academic conference8	2015～2015,00,00,,,	Physics-based Model for the Conductive Filament at the Low Resistance State of Thin SiO2 Films		JSAP Si Nanoelectronics WS	pp.79-80
37	International academic conference8	2015～2015,00,00,,,	Two-Dimensional Model for Asymmetric Double-Gate Tunnel FET Considering the Source-Channel Junction Depletion Region	International coauthorship	IEEE IMFEDK2015	pp.58-59
38	Papers1	2014～2014,00,00,,,	Analysis of soft failures in low-resistance interconnect via using doubly nesting arrays		IEEE TRANSACTIONS ON SEMICONDUCTOR MANUFACTURING	Volume:27 , Issue: 2 , p.178 - 183
39	International academic conference8	2014～2014,00,00,,,	Spectroscopic Electrical Characterization of Post-Resistive-Transition SiO2 Films		Tech. Dig., IEEE IMFEDK 2014	pp. 80-81
40	International academic conference8	2014～2014,00,00,,,	Characterization of Noise Behavior of Ultrathin Inversion-Channel and Buried-Channel SOI MOSFETs in the Subthreshold Bias Range,		Tech. Dig., IEEE IMFEDK 2014	pp. 46-47
41	International academic conference8	2014～2014,00,00,,,	Characterization and Modeling of Resistive-Transition Phenomena and Electronic Structure of Sputter-Deposition SiO2 Films		Tech. Dig., WOLTE-11	pp.69-72
42	International academic conference8	2014～2014,00,00,,,	Theoretical Modeling for Carrier Diffusion Coefficient in One-Dimensional Si Wires around Room Temperature		Proc. of IEEE Nanoelectron. Conf.	No. INEC-0135
43	International academic conference8	2014～2014,00,00,,,	Proposal of Simple Channel-Length-Dependent Current Model for Subthreshold Region of Nano-wire Tunnel FET		Tech. Dig., Compact Modeling,	pp. 28-31
44	International academic conference8	2013～2013,00,00,,,	Newly developed Test-Element-Group for detecting soft failures of the low-resistance-element using doublly nesting array		Proceedings of the 2013 IEEE International Conference on Microelectronic Test Structures	pp. 95 - 98
45	Papers1	2009～2009,00,00,,,	”Low-Temperature Behaviours of Phonon-Limited Electron Mobility of sub-10-nm-Thick Silicon-on-Insulator Metal-Oxide-Semiconductor Field-Effect Transistor with (001) and (111) Si Surface Channels		Japanese Journal of Applied Physics	vol. 48, pp. 071204-071211
46	Papers1	2008～2008,00,00,,,	Impact of Band Alignment on Line Electron Density and Channel Capacitance of Rectangular n-Channel Gate-All-Around Wire Field-Effect Transistor		Japanese Journal of Applied Physics	vol. 47, pp. 1706-1712
47	International academic conference8	2008～2008,00,00,,,	Low-Temperature Behavior Simulations of Phonon-Limited Electron Mobility for Sub-10-nm-Thick SOI MOSFET and GOI MOSFET with (111) or (001) Surface Channel,		Proc. The 8th Int. Workshop on Low Temperature Electronics (WOLTE) (Ilmenau, June, 2008)	pp. 69-70
48	Papers1	2007～2007,00,00,,,	Phonon-Limited Electron Mobility Behavior and Inherent Mobility Reduction Mechanism of Ultrathin Silicon-on-Insulator Layer with (111) Surface and Ultrathin Germanium-on-Insulator Layer with (001) Surface		Japanese Journal of Applied Physics	vol. 46, No. 12, pp. 7654-7661
49	Papers1	2007～2007,00,00,,,	Empirical Models of Phonon-Limited Electron Mobility for Ultra-Thin Body Single-Gate and Double-Gate Silicon-on-Insulator (SOI) Metal-Oxide-Semiconductor Field-Effect Transistors (MOSFETs) with (001) or (111) Si Surface Channel		Japanese Journal of Applied Physics	vol. 46, pp. 3463-3470
50	Papers1	2007～2007,00,00,,,	Features of Phonon-Limited Electron Mobility Behavior of Double-Gate Field-Effect Transistor with (111) Si Surface Channel		Applied Physics Letters	vol. 90, pp. 104103-104105
51	International academic conference8	2007～2007,00,00,,,	Important Aspects of Phonon-Limited Electron Mobility of Double-Gate Field-Effect Transistor or Fin FET with a (111) Si Surface Channel		2007 Int. Meet. Future Electron Devices, Kansai (IMFEDK) (Osaka, 2007)	pp. 23-24
52	Papers1	2007～2007,00,00,,,	Impact of Phonon- limited Mobility Superiority in Double-Gate or FinFET with a (111) Silicon and (001) Germanium Surface Channel on Device Scaling,		ECS Transactions	Vol. 6, No. 4, Silicon-on-Insulator Technol. and Dev. 13, pp. 369-374
53	Papers1	2007～2007,00,00,,,	Origin of Transient Gate Current Observed in Pseudo-MOS Transistor	International coauthorship	ECS Transactions	Vol. 6, No. 4, Silicon-on-Insulator Technol. and Dev. 13, pp. 95-100
54	International academic conference8	2007～2007,00,00,,,	Impact of Band Structure on Phonon-Limited Electron Mobility Behavior for Ultra-Thin GOI MOSFET		Abstr. IEEE 2007 Silicon Nanoelectronics WS (Kyoto, June, 2007)	pp. 35-36
55	International academic conference8	2007～2007,00,00,,,	Behavior of Low-Temperature Phonon-Limited Electron Mobility of Double-Gate Field-Effect Transistor with (111) Si Surface Channel,		Ext. Abstr. Int. Conf. Solid State Devices and Mat. (Tsukuba, Sep. 2007)	pp. 730-731
56	International academic conference8	2007～2007,00,00,,,	Low-Temperature Behavior Simulations of Phonon-Limited Electron Mobility for Sub-10-nm-Thick SOI MOSFET with (111) or (001) Si Surface Channel		Proc. IEEE 2007 Int. SOI Conf. (Indean Wells, Oct., 2007)	pp. 65-66
57	Papers1	2006～2006,00,00,,,	Quantum-Mechanical Suppression and Enhancement of Short-Channel Effects in Ultra-Thin SOI MOSFET’s		IEEE Trans. Electron Devices	vol. 53, pp. 677-684
58	Papers1	2006～2006,00,00,,,	Physics-Based Determination of the Carrier Effective Mass Assumed in Density Gradient Model		Japanese Journal of Applied Physics	vol. 45, pp. 689-693
59	International academic conference8	2006～2006,00,00,,,	Empirical Model of Phonon-Limited Electron Mobility for Ultra-Thin Body SOI MOSFET,		Ext. Abstr. Of 2006 Int. Conf. Solid State Devices and Mat. (Yokohama, 2006)	pp. 544-545
60	Papers1	2005～2005,00,00,,,	Possible Influence of the Schottky Contacts on the Characteristics of Ultra-Thin SOI Pseudo-MOS Transistors	International coauthorship	IEEE Trans. Electron Devices	vol. 52, pp. 1807-1814
61	Papers1	2005～2005,00,00,,,	Detailed Investigation of Geometrical Factor for Pseudo-MOS Transistor Technique	International coauthorship	IEEE Trans. Electron Devices	vol. 52, pp. 406-412
62	International academic conference8	2005～2005,00,00,,,	Impact of the Schottky Contact on Characterization of Ultra-thin SOI Pseudo-MOS Transistors	International coauthorship	Proc. 12th Int. Symp. Silicon-on-Insulator Technol. and Devices (The Electrochem. Soc., Canada, Quebec, 2005)	pp. 249-254
63	Papers1	2004～2004,00,00,,,	Impact of High-k Plug on Self-Heating Effects of SOI MOSFETs		IEEE Trans. Electron Devices	vol. 51, pp. 2249-2251
64	Papers1	2004～2004,00,00,,,	Engineering Source and Drain Diffusion for Sub-100-nm Channel Silicon-on-Insulator MOSFETs		IEEE Trans. Electron Devices	vol. 51, pp. 907-913
65	International academic conference8	2004～2004,00,00,,,	Quantum-Mechanical Enhancement of Short-Channel Effects in Ultra-Thin SOI MOSFETs		Ext. Abstr., IEEE 2004 Int. Meeting for Future Electron Dvices, Kansai (IMFEDK, Kyoto, July, 2004)	pp. 75-76
66	International academic conference8	2004～2004,00,00,,,	Detailed Investigation of Geomentrical Factor for Pseudo-MOS Transistor Technique	International coauthorship	Proc. 2004 IEEE Int. SOI Conf. (Charsten, USA, Oct. 2004)	pp. 75-76
67	International academic conference8	2004～2004,00,00,,,	Impact of high-k plug on self-heating effects of SOI MOSFET’s		Proc. the 4th Int. Symp. On Advanced Science and Technology of Silicon Materials (Kona, Hawaii, 2004) K-1	pp. 315-319
68	International academic conference8	2004～2004,00,00,,,	Impact of the Schottky contacts on characterization of Ultra-Thin SOI Pseudo-MOS transistors	International coauthorship	Proc. the 4th Int. Symp. On Advanced Science and Technology of Silicon Materials (Kona, Hawaii, 2004) K-6,	pp. 343-347.

PapersIn refereedCo-authored;2023/12～

International academic conferenceIn refereedCo-authored;;2023/11～

International academic conferenceIn refereedInternational coauthorship;;;;;2023/11～

International academic conferenceIn refereedCo-authored;2023/5～

International academic conferenceIn refereedCo-authored;2022/11～

International academic conferenceIn refereedSingle-AuthorSATO,Shingo2021/9～

PapersIn refereedCo-authored;;2021/9～

PapersIn refereedCo-authorMORI, Daigo;NAKATA, Iori;MATSUDA, Masayoshi;SATO, Shingo2021/4～

PapersIn refereedCo-authorOMURA, Yasuhisa;SATO,Shingo2021/1～

International academic conferenceIn refereedCo-authored;2020/8/31～2020/9/4

International academic conferenceIn refereedCo-authored;;2019/11～2019/11

PapersImpact of contact and channel resistance on the frequency-dependent capacitance and conductance of pseudo-MOSFETIn refereedInternational coauthorshipS. Sato;G. Ghibaudo;L. Benea;I. Ionica;Y. Omura;S. CristloveanuSolid State ElectronicsVol. 159, Sep. 2019, pp. 197-2032019/9～2019/9

PapersIn refereedCo-authored;;;2019/2～

PapersStudy on the Impacts of Hole Injection and Inclusion of Sub-oxide and Metallic Si Atoms on Repeatable Resistance Switching of Sputter-Deposited Silicon Oxide FilmsIn refereedCo-authoredY. Omura;R. Yamaguchi;S. SatoIEEE Transactions on Device and Materials ReliabilityVolume: 18, Issue:4, pp.561-5672018/12～

International academic conferenceSharp switching, hysteresis-free characteristics of Z2-FET for fast logic applicationsIn refereedInternational coauthorshipKH Lee;H El Dirani;P Fonteneau;M Bawedin;S Sato;S Cristoloveanu2018 48th European Solid-State Device Research Conference (ESSDERC)pp.74-772018/9～

International academic conferenceAspects and Reduction of Miller Capacitance of Lateral Tunnel FETsInternational coauthorshipY. Jiang;S. Sato;Y. Omura;A. MallikIEEE IMFEDK (Kyoto, 2018)pp.22-232018/6～

International academic conferenceDetailed analysis of frequency-dependent impedance in pseudo-MOSFET on thin SOI filmIn refereedInternational coauthorshipS. Sato;G. Ghibaudo;L. Benea;Y. Omura;S. CristoloveanuJoint International EUROSOI Workshop and International Conference on Ultimate Integration on Siliconpp. 89-902018/3～

PapersPossible Models of Electron-Energy Transfer in Resistance Switching by Sputter-Deposited Silicon Oxide Films: Potential of Extremely Low-Energy SwitchingIn refereedCo-authoredY. Omura;T. Akano;S. SatoECS Journal of Solid State Science and Technologyvolume 7, issue 3, Q21-Q252018/2～

PapersNovel Addressable Test Structure for Detecting Soft Failure of Resistive Elements when Developing Manufacturing ProceduresIn refereedCo-authorS. Sato;Y. OmuraIEEE Transactions on Semiconductor ManufacturingVol. 31, Issue. 1, pp.124-1292018～

International academic conferenceMeasuring impact of light on resistance of non-doped ZnO filmsIn refereedCo-authoredN. Takahashi;S. Sato;Y. Omura;T. SaitohAdvanced NanoMaterials Conf., (Aveiro, Portugal, 2018)in print2018～

PapersRevisiting the Role of Trap-Assisted-Tunneling Process on Current-Voltage Characteristics in Tunnel Field-Effect TransistorsIn refereedInternational coauthorshipY. Omura;Y. Mori;S. Sato;A. MallikJournal of Applied Physicsvol. 123, pp. 161549-1-161549-6 2017/12～

International academic conferencePhysical Mechanisms of Short-Channel Effects of Lateral Double-Gate Tunnel FETIn refereedInternational coauthorshipY. Mori;S. Sato;Y. Omura;A. MallikProceedings of Nano S & T 2017p.55252017/10～

International academic conferenceTheoretical Models for Electron Diffusion Coefficient of One-Dimensional Si Wire Devices: impacts of conduction band non-parabolicity-In refereedCo-authoredY. Omura;S. SatoProceedings of Nano S & T 2017p.3382017/10～

International academic conferenceImportant Roles of Hole Injection and Inclusion of Sub-oxide and Metallic Si Atoms on Resistive Transition of Sputter-Deposited Silicon Oxide FilmsIn refereedCo-authoredY. Omura;R. Yamaguchi;S. SatoProceedings of Nano S & T 2017pp. 3462017/10～

International academic conferenceTheoretical Models for Low-Frequency Noise Behaviors of Buried-Channel MOSFETsIn refereedCo-authoredY. Omura;S. SatoProc. IEEE S3S Conference 2017 (Oct., San Francisco)paper No. 8.112017/10～

Academic presentationDefinite Influence of Substrate-contact Condition on SOI Substrate Impedance ParametersIn refereedCo-authoredI. Yarita;S. Sato;Y. OmuraProc. IEEE S3S Conference 2017 (Oct., San Francisco)paper No. 8. 7.2017/10～

International academic conferenceImpact of Crystal Orientation and Conduction Band Non-parabolicity on Diffusion Constant of Nano-scale Si Rectangular Wires - theoretical estimationIn refereedCo-authoredY. Omura;S. Sato12th Nanosmat Conf. (Paris, Sept., 2017)pp. 1-32017/9～

Academic presentationUnrefereedInternational coauthorship2017/9～

Academic presentationUnrefereedCo-authored2017/9～

PapersImpact of Native Oxide Growth on the Capacitance-Voltage Characteristic of Pseudo-MOS StructureIn refereedCo-authoredI. Yarita;S. Sato;Y. OmuraECS Transactionsvol. 77, issue 11, pp. 1887-18922017/7～

PapersOn the Definition of Threshold Voltage for Tunnel FETsIn refereedInternational coauthorshipY. Mori;S. Sato;Y. Omura;A. Chattopadhyay;A. MallikSuperlattices and Microstructuresvol. 107, pp. 17-272017/4～

PapersRoles of chemical stoichiometry and hot electrons in realizing the stable resistive transition of sputter-deposited silicon oxide filmsIn refereedCo-authoredR. Yamaguchi;S. Sato;Y. OmuraJapanese Journal of Applied Physicsvol. 56, No. 4, pp. 041301-1-041301-62017/3～

International academic conferenceImpact of native oxide on the capacitance-voltage characteristic for pseudo-MOS structureIn refereedCo-authoredI. Yarita;S. Sato;Y. OmuraThe 231st Electrochemical Society MeetingAbstract MA2017-01, Z01-19592017/3～

International academic conferenceRecent Progress of Pseudo-MOS Method Used for Evaluating Electrical Properties of the SOI WaferIn refereedCo-authoredS. Sato;I. Yarita;Y. OmuraProc. 4th int. Symp. Semicond. Mat. And Devicespp. 342017/3～

Academic presentationUnrefereedCo-authored2017/3～

Academic presentationUnrefereedInternational coauthorship2017/3～

Academic presentationUnrefereedInternational coauthorship8a-C15-12017/3～

International academic conferenceProposal of a New Array Structure to Enable the Detection of Soft Failure and the Aging Test with Overcurrent of Resistive ElementIn refereedS. Sato;Y. OmuraProceedings of 29th IEEE International Conference on Microelectronic Test Structurespp.52-562016～

PapersProposal of Physics-Based Equivalent Circuit of Pseudo-MOS Capacitor Structure for Impedance SpectroscopyIn refereedI. Yarita;S. Sato;Y. OmuraIEEE Journal of the Electron Devices Societyvol. 4, pp. 169-1732016～

International academic conferenceStable Unipolar and Bipolar Resistive Transitions of Sputter-Deposited SiO2 FilmsIn refereedR. Yamaguchi;T. Akano;S. Sato;Y. OmuraAbstracts of 2016 IEEE Silicon Nanoelectronics WSpp. 74-752016～

International academic conferenceA Possible Threshold Voltage Definition of Lateral Tunnel FET,In refereedInternational coauthorshipY. Mori;S. Sato;Y. Omura;A. mallikAbstracts of 2016 IEEE Silicon Nanoelectronics WSpp. 188-1892016～

International academic conferenceCapacitance Analysis of Pseudo-MOSFET Using Cole-Cole PlotsIn refereedI. Yarita;S. Sato;Y. OmuraTech. Digest of IEEE IMFEDK 2016pp. 36-37.2016～

International academic conferenceSensitivity of Resistive Transition of Sputter-Deposited TiO2 Films to Electrode MaterialIn refereedN. Kawashima;S. Sato;Y. OmuraTech. Dig. of IEEE IMFEDK 2016pp. 72-73.2016～

Academic presentationUnrefereed2016～

PapersPossible Theoretical Models for Carrier Diffusion Coefficient of One-Dimensional Si Wire DevicesIn refereedS. Sato;Y. OmuraJapanese Journal of Applied Physicsvol.54, No. 5, p.054001-1-054001-72015～

PapersCompact Modeling for Nano-Wire Tunnel Field-Effect TransistorIn refereedInternational coauthorshipS. Sato;Y. Omura;A. MallikECS Transactionsvol. 66, No. 5, pp.171-1772015～

PapersAnalytically Modeling the Asymmetric Double Gate Tunnel FETIn refereedInternational coauthorshipH. Lv;S. Sato;Y. Omura;A. MallikECS Transactionsvol. 66, No. 5, pp.193-2002015～

International academic conferenceCircuit Architecture and Measurement Technique to Reduce the Leakage Current Stemming from Peripheral Circuits with an Array Structure in Examining the Resistive ElementIn refereedS. Sato;T. Ito;Y. OmuraProceedings of the 2015 IEEE International Conference on Microelectronic Test Structurespp.14-172015～

International academic conferenceCompact Modeling for Nano-Wire Tunnel Field Effect TransistorIn refereedS. Sato;Y. Omura;A. Mallik227th ECS Meeting, Int. Symp. on Advanced CMOS-Compatible Semiconductor Devices 17thNo. 462972015～

International academic conferenceAn Analytical Modeling for Asymmetric Double-Gate Tunnel FET OperationIn refereedInternational coauthorshipH. Lv;S. Sato;Y. Omura;A. Mallik227th ECS Meeting, Int. Symp. on Advanced CMOS-Compatible Semiconductor Devices 17thNo. 494342015～

International academic conferenceTwo-Dimensional Potential Model for Asymmetric Double-Gate Tunnel FET Considering the Source-Channel Junction Depletion RegionIn refereedInternational coauthorshipH. Lv;S. Sato;Y. Omura;A. MallikTech. Dig., IEEE IMFEDKpp.58-592015～

International academic conference Development of a Compacted Doubly Nesting Array in Narrow Scribe Line Aimed at Detecting Soft Failures of Interconnect ViaH. Shinkawata;N. Tsuboi;A. Tsuda;S. Sato;Y. Yamaguchi28th IEEE International Conference on Microelectronic Test Structurespp.78-812015～

Academic presentationUnrefereed2015～

International academic conferencePhysics-based Model for the Conductive Filament at the Low Resistance State of Thin SiO2 FilmsR. Yamaguchi;S. Sato;Y. OmuraJSAP Si Nanoelectronics WSpp.79-802015～

International academic conferenceTwo-Dimensional Model for Asymmetric Double-Gate Tunnel FET Considering the Source-Channel Junction Depletion RegionInternational coauthorshipH. Lv;S. Sato;Y. Omura;A. MallikIEEE IMFEDK2015pp.58-592015～

PapersAnalysis of soft failures in low-resistance interconnect via using doubly nesting arraysIn refereedH. Shinkawata;S. Sato;A. Tsuda;T. Yoshizawa;T. OhnoIEEE TRANSACTIONS ON SEMICONDUCTOR MANUFACTURINGVolume:27 , Issue: 2 , p.178 - 1832014～

International academic conferenceSpectroscopic Electrical Characterization of Post-Resistive-Transition SiO2 FilmsIn refereedR. Yamaguchi;S. Sato;Y. Omura;K. NakamuraTech. Dig., IEEE IMFEDK 2014pp. 80-812014～

International academic conferenceCharacterization of Noise Behavior of Ultrathin Inversion-Channel and Buried-Channel SOI MOSFETs in the Subthreshold Bias Range,In refereedT. Ito;S. Sato;Y. OmuraTech. Dig., IEEE IMFEDK 2014pp. 46-472014～

International academic conferenceCharacterization and Modeling of Resistive-Transition Phenomena and Electronic Structure of Sputter-Deposition SiO2 FilmsIn refereedR. Yamaguchi;S. Sato;Y. Omura;K. NakamuraTech. Dig., WOLTE-11pp.69-722014～

International academic conferenceTheoretical Modeling for Carrier Diffusion Coefficient in One-Dimensional Si Wires around Room TemperatureIn refereedY. Omura;S. SatoProc. of IEEE Nanoelectron. Conf.No. INEC-01352014～

International academic conferenceProposal of Simple Channel-Length-Dependent Current Model for Subthreshold Region of Nano-wire Tunnel FETIn refereedS. Sato;Y. Omura;A. MallikTech. Dig., Compact Modeling,pp. 28-312014～

Academic presentationUnrefereed2014～

Academic presentationUnrefereedOther2014～

Academic presentationUnrefereedInternational coauthorship2014～

International academic conferenceNewly developed Test-Element-Group for detecting soft failures of the low-resistance-element using doublly nesting arrayIn refereedS. Sato;H. Shinkawata;A. Tsuda;T. Yoshizawa;T. OhnoProceedings of the 2013 IEEE International Conference on Microelectronic Test Structurespp. 95 - 982013～

Academic presentationUnrefereedInternational coauthorshipOMURA,Yasuhisa;SATO,Daiki;SATO,Shingo;Abhijit Mallik2013～

Papers”Low-Temperature Behaviours of Phonon-Limited Electron Mobility of sub-10-nm-Thick Silicon-on-Insulator Metal-Oxide-Semiconductor Field-Effect Transistor with (001) and (111) Si Surface ChannelsY. Omura;T. Yamamura;S. SatoJapanese Journal of Applied Physicsvol. 48, pp. 071204-0712112009～

PapersImpact of Band Alignment on Line Electron Density and Channel Capacitance of Rectangular n-Channel Gate-All-Around Wire Field-Effect TransistorIn refereedS. Sato;Y. OmuraJapanese Journal of Applied Physicsvol. 47, pp. 1706-17122008～

International academic conferenceLow-Temperature Behavior Simulations of Phonon-Limited Electron Mobility for Sub-10-nm-Thick SOI MOSFET and GOI MOSFET with (111) or (001) Surface Channel,In refereedT. Yamamura;S. Sato;Y. OmuraProc. The 8th Int. Workshop on Low Temperature Electronics (WOLTE) (Ilmenau, June, 2008)pp. 69-702008～

PapersPhonon-Limited Electron Mobility Behavior and Inherent Mobility Reduction Mechanism of Ultrathin Silicon-on-Insulator Layer with (111) Surface and Ultrathin Germanium-on-Insulator Layer with (001) SurfaceT. Yamamura;S. Sato;Y. OmuraJapanese Journal of Applied Physicsvol. 46, No. 12, pp. 7654-76612007～

PapersEmpirical Models of Phonon-Limited Electron Mobility for Ultra-Thin Body Single-Gate and Double-Gate Silicon-on-Insulator (SOI) Metal-Oxide-Semiconductor Field-Effect Transistors (MOSFETs) with (001) or (111) Si Surface ChannelT. Yamamura;S. Sato;Y. OmuraJapanese Journal of Applied Physicsvol. 46, pp. 3463-34702007～

PapersFeatures of Phonon-Limited Electron Mobility Behavior of Double-Gate Field-Effect Transistor with (111) Si Surface ChannelT. Yamamura;S. Sato;Y. OmuraApplied Physics Lettersvol. 90, pp. 104103-1041052007～

International academic conferenceImportant Aspects of Phonon-Limited Electron Mobility of Double-Gate Field-Effect Transistor or Fin FET with a (111) Si Surface ChannelIn refereedT. Yamamura;S. Sato;Y. Omura2007 Int. Meet. Future Electron Devices, Kansai (IMFEDK) (Osaka, 2007)pp. 23-242007～

PapersImpact of Phonon- limited Mobility Superiority in Double-Gate or FinFET with a (111) Silicon and (001) Germanium Surface Channel on Device Scaling,In refereedT. Yamamura;S. Sato;Y. OmuraECS TransactionsVol. 6, No. 4, Silicon-on-Insulator Technol. and Dev. 13, pp. 369-3742007～

PapersOrigin of Transient Gate Current Observed in Pseudo-MOS TransistorIn refereedInternational coauthorshipS. Sato;N. Q. Tuan;S. Cristoloveanu;Y. OmuraECS TransactionsVol. 6, No. 4, Silicon-on-Insulator Technol. and Dev. 13, pp. 95-1002007～

International academic conferenceImpact of Band Structure on Phonon-Limited Electron Mobility Behavior for Ultra-Thin GOI MOSFETIn refereedT. Yamamura;S. Sato;Y. OmuraAbstr. IEEE 2007 Silicon Nanoelectronics WS (Kyoto, June, 2007)pp. 35-362007～

International academic conferenceBehavior of Low-Temperature Phonon-Limited Electron Mobility of Double-Gate Field-Effect Transistor with (111) Si Surface Channel,In refereedT. Yamamura;S. Sato;Y. OmuraExt. Abstr. Int. Conf. Solid State Devices and Mat. (Tsukuba, Sep. 2007)pp. 730-7312007～

International academic conferenceLow-Temperature Behavior Simulations of Phonon-Limited Electron Mobility for Sub-10-nm-Thick SOI MOSFET with (111) or (001) Si Surface ChannelIn refereedT. Yamamura;S. Sato;Y. OmuraProc. IEEE 2007 Int. SOI Conf. (Indean Wells, Oct., 2007)pp. 65-662007～

PapersQuantum-Mechanical Suppression and Enhancement of Short-Channel Effects in Ultra-Thin SOI MOSFET’sY. Omura;H. Konishi;S. SatoIEEE Trans. Electron Devicesvol. 53, pp. 677-6842006～

PapersPhysics-Based Determination of the Carrier Effective Mass Assumed in Density Gradient ModelS. Sato;Y. OmuraJapanese Journal of Applied Physics vol. 45, pp. 689-6932006～

International academic conferenceEmpirical Model of Phonon-Limited Electron Mobility for Ultra-Thin Body SOI MOSFET,In refereedT. Yamamura;S. Sato;Y. OmuraExt. Abstr. Of 2006 Int. Conf. Solid State Devices and Mat. (Yokohama, 2006)pp. 544-5452006～

PapersPossible Influence of the Schottky Contacts on the Characteristics of Ultra-Thin SOI Pseudo-MOS TransistorsInternational coauthorshipS. Sato;K. Komiya;N. Bresson;Y. Omura;S. CristoloveanuIEEE Trans. Electron Devicesvol. 52, pp. 1807-18142005～

PapersDetailed Investigation of Geometrical Factor for Pseudo-MOS Transistor TechniqueInternational coauthorshipK. Komiya;N. Bresson;S. Sato;S. Cristoloveanu;Y. OmuraIEEE Trans. Electron Devicesvol. 52, pp. 406-4122005～

International academic conferenceImpact of the Schottky Contact on Characterization of Ultra-thin SOI Pseudo-MOS TransistorsIn refereedInternational coauthorshipS. Sato;K. Komiya;N. Bresson;Y. Omura;S. CristoloveanuProc. 12th Int. Symp. Silicon-on-Insulator Technol. and Devices (The Electrochem. Soc., Canada, Quebec, 2005)pp. 249-2542005～

PapersImpact of High-k Plug on Self-Heating Effects of SOI MOSFETsK. Komiya;T. Kawamoto;S. Sato;Y. OmuraIEEE Trans. Electron Devicesvol. 51, pp. 2249-22512004～

PapersEngineering Source and Drain Diffusion for Sub-100-nm Channel Silicon-on-Insulator MOSFETsA. Kawamoto;S. Sato;Y. OmuraIEEE Trans. Electron Devicesvol. 51, pp. 907-9132004～

International academic conferenceQuantum-Mechanical Enhancement of Short-Channel Effects in Ultra-Thin SOI MOSFETsIn refereedH. Konishi;S. Sato;K. Komiya;Y. OmuraExt. Abstr., IEEE 2004 Int. Meeting for Future Electron Dvices, Kansai (IMFEDK, Kyoto, July, 2004)pp. 75-762004～

International academic conferenceDetailed Investigation of Geomentrical Factor for Pseudo-MOS Transistor TechniqueIn refereedInternational coauthorshipProc. 2004 IEEE Int. SOI Conf. (Charsten, USA, Oct. 2004)pp. 75-762004～

International academic conferenceImpact of high-k plug on self-heating effects of SOI MOSFET’sIn refereedK. Komiya;T. Kawamoto;S. Sato;Y. OmuraProc. the 4th Int. Symp. On Advanced Science and Technology of Silicon Materials (Kona, Hawaii, 2004) K-1pp. 315-3192004～

International academic conferenceImpact of the Schottky contacts on characterization of Ultra-Thin SOI Pseudo-MOS transistorsIn refereedInternational coauthorshipS. Sato;K. Komiya;N. Bresson;Y. Omura;S. CristoloveanuProc. the 4th Int. Symp. On Advanced Science and Technology of Silicon Materials (Kona, Hawaii, 2004) K-6,pp. 343-347.2004～

SATO, Shingo

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